SN74AHCT74QDRG4Q1_TI(德州仪器)中文资料_英文资料_价格_PDF手册

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· Qualified for Automotive Applications

· Inputs Are TTL-Voltage Compatible

· EPIC (Enhanced-Performance Implanted CMOS) Process

· Latch-Up Performance Exceeds 250 mA Per JESD 17

· ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Description

The SN74AHCT74Q is a dual positive-edge-triggered D-type flip-flop.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.