SN74AHC74QPWRQ1具有清零和预设功能的汽车类双路上升沿 D 类触发器

·Qualified for Automotive Applications

·EPIC (Enhanced-Performance Implanted CMOS) Process

·Operating Range 2-V to 5.5-V VCC

·Latch-Up Performance Exceeds 250 mA Per JESD 17

·ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Description

The SN74AHC74Q dual positive-edge-triggered device is a D-type flip-flop.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.