W25Q128JVSIQ

IC FLASH 128MBIT SPI/QUAD 8SOIC

1. GENERAL DESCRIPTIONS

The W25Q128JV (128M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 1µA for power-down. All devices are offered in space-saving packages.

The W25Q128JV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128JV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.)

The W25Q128JV supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 and I/O3. SPI clock frequencies of W25Q128JV of up to 133MHz are supported allowing equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories.

Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP, and a 64-bit Unique Serial Number and three 256-bytes Security Registers.

2. FEATURES

· New Family of SpiFlash Memories

W25Q128JV: 128M-bit / 16M-byte

Standard SPI: CLK, /CS, DI, DO

Dual SPI: CLK, /CS, IO0, IO1

Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3

Software & Hardware Reset(1)

Highest Performance Serial Flash

133MHz Single, Dual/Quad SPI clocks

266/532MHz equivalent Dual/Quad SPI

66MB/S continuous data transfer rate

Min. 100K Program-Erase cycles per sector

More than 20-year data retention

· Efficient “Continuous Read”

Continuous Read with 8/16/32/64-Byte Wrap

As few as 8 clocks to address memory

Allows true XIP (execute in place) operation

· Low Power, Wide Temperature Range

Single 2.7 to 3.6V supply

<1µA Power-down (typ.)

-40°C to +85°C operating range

-40°C to +105°C operating range

Flexible Architecture with 4KB sectors

Uniform Sector/Block Erase(4K/32K/64K-byte)

Program 1 to 256 byte per programmable page

Erase/Program Suspend & Resume

Advanced Security Features

Software and Hardware Write-Protect

Power Supply Lock-Down

Special OTP protection

Top/Bottom, Complement array protection

Individual Block/Sector array protection

64-Bit Unique ID for each device

Discoverable Parameters (SFDP) Register

3X256-Bytes Security Registers with OTP locks

Volatile & Non-volatile Status Register Bits

· Space Efficient Packaging

8-pin SOIC 208-mil

16-pin SOIC 300-mil (additional /RESET pin)

9-pad WSON 6x5-mm / 8x6-mm

24-ball TFBGA 8x6-mm (6x4/5x5 ball array)

24-ball WLCSP

Contact Winbond for KGD and other options

3. PACKAGE TYPES AND PIN CONFIGURATIONS

4. PIN DESCRIPTIONS

4.1 Chip Select (/CS)

The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure 58). If needed a pull-up resister on the /CS pin can be used to accomplish this.

4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)

The W25Q128JV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK.

Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and the /HOLD pin becomes IO3.

4.3 Write Protect (/WP)

The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low.

4.4 HOLD (/HOLD)

The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See Figure 1a-c for the pin configuration of Quad I/O operation.

4.5 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations")

4.6 Reset (/RESET)

A dedicated hardware /RESET pin is available on SOIC-16 and TFBGA packages. When it’s driven low for a minimum period of ~1µS, this device will terminate any external or internal operations and return to its power-on state.

5. BLOCK DIAGRAM