ADC3244EVM

EVAL MODULE FOR ADC3244

This document is a user’s guide for the ADC3xxxEVM and ADC3xJxxEVM. The EVMs provide a platform for evaluating the ADC3xxx and ADC3xJxx. The ADC3xxx is a dual-channel or quad-channel, 12-bit or 14- bit, serial LVDS interface analog-to-digital converter (ADC). The ADC3xxx comes with sampling speed grades of 25 MSPS, 50 MSPS, 80 MSPS, and 125 MSPS. The ADC3xJxx is a dual-channel or quadchannel, 12-bit or 14-bit, JESD204B-compliant interface ADC. The ADC3xJxx comes with sampling speed grades of 50 MSPS, 80 MSPS, 125 MSPS, and 160 MSPS. This family of converters requires only a single 1.8-V supply, provides flexible input clock dividers, and provides internal features for improved 1/f (ADC32xx, ADC34xx) and SFDR performance. Throughout this document, the abbreviations EVM and ADC3xxxx, and the term evaluation module are synonymous with the ADC3xxx EVM and ADC3xJxx EVM, unless otherwise noted

1 Introduction

There are three package sizes and pinouts for all of these parts. The sLVDS dual devices use a 7-mm × 7-mm, 48-pin QFN package. The sLVDS quad devices use an 8-mm × 8-mm, 56-pin QFN package. The dual and quad JESD204B device share the same package using a 7-mm × 7-mm, 48-pin QFN package 

The dual ADCs comprise two buffered inputs, two ADC cores, and a common input clock circuit. The quad ADCs comprise four buffered inputs, four ADC cores, and a common input clock circuit. The sLVDS versions have a 2-wire interface per ADC (two pairs of p/n signals)—for the dual, this means two sets of 2- wire interfaces (four p/n pairs), the quad has four sets of 2-wire interfaces (eight p/n pairs). Each of these 2-wire interfaces can be operated in 1-wire mode (14x serialization), or 2-wire mode (7x serialization). For the 12-bit devices, this equates to 12x and 6x serialization. The JESD204B versions have one lane per ADC core. For the dual, this means there are two lanes per device, and four lanes per device for the quad. See the respective device data sheet for more information on sLVDS serialization and JESD204B lane configurations.

1.1 EVM Block Diagram

Figure 1 and Figure 2 show simplified block diagrams of the default configuration of the EVM. The two or four analog inputs are supplied to the EVM through a single-ended SMA connection, then transformer coupled to turn the single-ended signal into a balanced differential signal, and then input to the ADC32xxx or ADC34xxx. A dual transformer input circuit is used for better phase and amplitude balance of the input signal than is typically produced by a single transformer input circuit.

1.2 EVM Power Supply

Figure 3 illustrates the power supply options available on the ADC3xxx EVM. Jumpers are used to choose the power-supply options, with the default jumper positions indicated by the darker portion of the jumper that represents the presence of the jumper. See Table 2 for jumper and feedback resistor configuration.

1.3 EVM Connectors and Jumpers

Figure 4 and Figure 5 show the locations of the connectors, jumpers, pushbutton switches, and LEDs

The EVM has a barrel connector for 5-V power. The SMA connectors connect the ADC input and ADC clock input to the ADC. Typically, the ADC inputs are transformer-coupled to accept single-ended connections. The input circuit can be configured to connect to two SMA connectors for differential signaling, if desired. Table 3 lists the connector information for the ADC3xxxx