LP5912DRV18EVM

EVAL BOARD FOR LP5912

1 Introduction

The Texas Instruments LP5912DRV EVM evaluation module (EVM) helps designers evaluate the operation and performance of the LP5912 LDO voltage regulator. The LP5912DRV EVM contains one LP5912 LDO voltage regulator in the WSON (DRV) package .

2 Setup

This section describes the jumpers and connectors on the EVM, as well and how to properly connect, set up and use the LP5912DRV EVM.

The device has been designed to work with 1-µF input and output ceramic capacitors down to 0603 component size.

2.1 Input/Output Connector Descriptions

VIN and GNDIN are the connection terminals for the input supply. The VIN terminal is the positive connection, and the GNDIN terminal is the negative (that is, ground) connection.

VOUT and GNDOUT are the connection terminals for the output load. The VOUT terminal is the positive connection, and the GNDOUT terminal is the negative (that is, ground) connection.

The PG test terminal is the connection used to monitor the status of the LP5912 Power Good) (PG) pin. The PG pin is an open drain connection which requires pull-up to some outside voltage, either VIN or VOUT, through a current limiting resistor. When the PG test terminal is a logic ‘high’ the output voltage is ‘good’. When the PG test terminal is a logic ‘low’, the output voltage is ‘not good’.

OUT_PG_IN is a 3-pin terminal strip used to select the PG (Power Good) pull-up bias source. The placement of a shunt allows either the input supply (VIN) or the LP5912 regulated output voltage (VOUT) to be used.

When the shunt is across the OUT_PG terminal pins the PG pin is connected through a 10-kΩ pull-up resistor to VOUT. When the shunt is across the PG_IN terminal pins the PG pin is connected through a 10-kΩ pull-up resistor to VIN.

The default, and recommended, shunt position is across the OUT_PG terminal pins to use VOUT for the pull-up bias.

GND_EN_IN is a 3-pin terminal strip used to enable, or disable, the LP5912.

When the shunt is across the EN_IN terminal pins the Enable (EN) pin is connected directly to VIN. The LP5912 will be enabled when VIN is applied. When the shunt is across the IN_GND terminal pins the Enable (EN) pin is connected directly to GND. The LP5912 will be disabled.

The shunt must be in place, or the EN terminal pin must be driven by an off board power supply, otherwise the LP5912 EN pin is floating, and the EN status may be undefined. The default, and recommended, shunt position is across the EN_IN terminal pins (enabled). When driving the EN terminal with an off-board supply or signal generator, the applied voltage must be kept between 0 V and 5.5 V.

2.2 Setup

The recommended operating input voltage range for the LP5912DRV EVM is VOUT + 0.5 V (minimum) to 6.5 V (maximum).

A load should be applied between the VOUT terminal and the GNDOUT terminal for proper operation. Load current should be maintained between 1 mA and 500 mA.

A digital voltmeter can be connected to the PG test terminal to monitor the PG status.

2.3 Operation

For proper operation of the LP5912DRV EVM, the two jumper terminals should be properly configured. The recommended jumper settings are:

OUT_PG_IN shunt across the OUT_PG pins.

GND_EN_IN shunt across the EN_IN pins.

In this configuration, the device will power up when power is applied at the VIN terminal, and VOUT will be used for the PG pin pull-up source.

2.4 Options

The LP5912DRV EVM has some assorted unpopulated footprints that some users may find useful:

• Footprint for and optional input capacitor at C4 (0805)

• Footprints for optional output capacitors at C1 (0603), C2 (0603), and C3 (0805)

• Footprints for optional SMA connectors (Emerson 142-0701-851, or eqivalent) at VIN (J2) and VOUT (J1) for noise or PSRR testing.

3 Board Layout

Figure 5 through Figure 10 show the board layout for the LP5912DRV EVM PCB. The EVM offers resistors, capacitors, and 3-pin terminals, to program the Enable pin status and to select the PG pin pullup source.

The LP5912 will dissipate power. The WSON DRV 6-pin package offers an exposed thermal pad to enhance thermal performance. The exposed thermal pad must be soldered to the copper landing on the PCB for optimal thermal performance. The PCB provides 1 oz. (0.0014 inch) copper planes on all four layers to dissipate heat.