PCM4204EVM

EVALUATION MODULE FOR PCM4204

This document provides the information needed to set up and operate the PCM4204EVM evaluation module (EVM). For a more detailed description of the PCM4204, please refer to the product datasheet available from the Texas Instruments web site at http://www.ti.com. Additional support documents are listed in the sections of this guide entitled Related Documentation from Texas Instruments and Additional Documentation. Throughout this document, the acronym EVM and the phrase evaluation module are synonymous with the PCM4204EVM. This user's guide includes setup and configuration instructions, information regarding absolute operating conditions for power supplies and input/output connections, an electrical schematic, PCB layout drawings, and a bill of materials (BOM) for the EVM.

1 Introduction

The PCM4204 is a high-performance, four-channel audio analog-to-digital (A/D) converter designed for use in professional and broadcast audio applications. The PCM4204 features simultaneous 24-bit linear PCM or 1-bit Direct Stream Digital (DSD) data output for all four channels. Sampling rates up to 216kHz are supported for PCM output formats, while 64x or 128x oversampled 1-bit data is supported for DSD output and input modes. Native support for both PCM and DSD data formats makes the PCM4204 ideal for use in a variety of audio recording and processing applications.

The PCM4204 features 1-bit delta-sigma (ΔΣ) modulators employing a novel density modulated dithering scheme, yielding improved dynamic performance. Differential voltage inputs are utilized for the modulators, providing excellent common-mode rejection. On-chip voltage references are provided for the modulators, in addition to generating DC common-mode bias voltage outputs for use with external input circuitry. Linear phase digital decimation filtering is provided for the 24-bit PCM output, with a minimum stop band attenuation of -100dB for all sampling modes.

The PCM output mode features clipping flag outputs for each of the four channels, as well as a digital high-pass filter for DC removal. The PCM4204 is configured using dedicated input pins for sampling mode and audio data format selection, high-pass filter enable/disable, and reset/power-down operation.

A +5V power supply is required for the analog section of the device, while a +3.3V power supply is required for the digital circuitry. Figure 1 shows the functional block diagram of the PCM4204.

1.1 PCM4204EVM Features

The PCM4204EVM provides a convenient platform for evaluating the performance and functionality of the PCM4204 product. The primary EVM features include:

• Simple configuration using onboard DIP switches

• Four differential voltage inputs supporting either 3-pin XLR or Balanced TRS connections

• Low-noise input buffer circuits utilizing the OPA1632 fully differential audio amplifier

• Four 75Ω AES3-encoded outputs, supporting operation up to 216kHz sampling rates

• Buffered Audio Serial Port supports a four-channel, 24-bit linear PCM data interface for external hardware and signal processors. Sampling rates up to 216kHz are supported.

• DSD Data Port supports a four-channel, 1-bit output or input data interface at 64x or 128x data rates

• A second PCM4204 provides a test mode for 1-bit DSD to 24-bit linear PCM format conversions

• Two onboard system clock oscillators, operating at 22.5792MHz and 24.576MHz respectively, supporting standard PCM sampling rates, including 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, and 192kHz.

• External system clock inputs supporting alternative sampling rates up to 216kHz. The PCM4204EVM requires +15V, -15V, and +5V analog power supplies. Additionally, a +5V digital power supply is required, with a +3.3V digital supply being derived onboard using a linear voltage regulator IC.

1.2 PCM4204EVM General Description and Functional Block Diagram

The PCM4204EVM provides a complete platform for evaluating the performance and features of the PCM4204 four-channel audio A/D converter. Figure 2 illustrates the functional block diagram for the evaluation module.

Four differential analog inputs are supported at connectors J1 through J4, corresponding to analog input channels 1 through 4, respectively. These connectors support either 3-pin male XLR or balanced TRS input plugs. Each of the analog inputs is buffered and filtered using a low noise input circuit, utilizing a Texas Instruments OPA1632 fully differential amplifier. The output of each buffer circuit is connected to a corresponding differential input of the PCM4204 (U1). The PCM4204 is then used to convert the analog signal to either a 24-bit linear PCM or 1-bit DSD representation in the digital domain.

The 24-bit PCM data output is made available at header J6, or at the AES3-encoded data outputs provided at jacks J9 through J12. The buffered header is convenient for interfacing to external development hardware or digital signal processors, while the AES3-encoded outputs may be connected to audio test systems or commercial audio equipment.

The 1-bit DSD data is available at header J7. This header is bi-directional, and may be used for either DSD output or input mode operation. A second PCM4204 (U2) is included for supporting a DSD-to-PCM format conversion test or demo mode. The resulting PCM-formatted output data is made available at header J8.

Power is connected to the board at either terminal block J5 for the analog supplies, or at terminal block J14 for the digital supplies.

Manual reset circuits are provided for both the PCM4204 (U1 and U2) and the AES3 transmitters (U18 through U21). The ADC RESET switch (SW2) is utilized for resetting the A/D converters (U1 and U2), while the DIT RESET switch (SW4) is utilized for resetting the AES3 transmitters (U18 through U21).

The system or master clock for the evaluation module may be generated onboard or by an external clock source. Oscillators X1 and X2 operate at fixed clock frequencies of 22.5792MHz and 24.576MHz, respectively. The oscillators provide low jitter clock sources for measuring the performance of the PCM4204 in Master mode operation. Alternatively, an external clock source may be connected at J13 for Master mode operation, supporting alternate system clock and sampling frequencies. For Slave mode operation, the system clock is provided from an external source through header J6 and buffer U12. Switch SW5 provides clock configuration control for the oscillators and the external clock input at connector J13.